The present invention relates to a transistor design, and more specifically, to a design of printed organic transistors for addressing an electronic display.
It is advantageous to include one or more thin film transistor(s) at each pixel in the circuitry for electronic addressing of some displays. Most notably, active matrix drive schemes usually include a thin-film transistor (TFT) at each pixel. The TFT acts as a non-linear element on the backplane of a display and permits application of advantageous electronic signals at each pixel for driving a display. For example, active matrix backplanes are routinely used to drive liquid crystal displays, especially those with a large number of rows and columns of pixels.
Enhancement mode field effect transistors (FETs) are well known. In an enhancement mode FET, no current flows between the source and the drain of the FET when zero potential or voltage is applied to the gate terminal. The current increases as the magnitude of the gate voltage is increased in the appropriate sense, by virtue of the presence of mobile charges induced within the channel. Depletion mode FETs are also known, in which the maximum conductivity, and hence current flow, occurs for zero applied gate voltage, and an increase in the gate voltage in the appropriate sense causes the source-drain current to diminish by virtue of a reduction of the free carrier charge density within the channel. Applying small voltages of the inappropriate sense to either device has an insignificant effect on the device. Applying large voltages of either sense can damage the device permanently. Depletion mode FETs can operate in enhancement mode if moderate gate voltages of the xe2x80x9cwrongxe2x80x9d or xe2x80x9creversexe2x80x9d polarity are applied to them, because the reverse gate voltage induces additional mobile charges into the channel of the FET. However, reversed gate voltages applied to enhancement mode FETs cannot significantly reduce the already insignificant number of mobile carriers, so no readily observable response is forthcoming.
Two carrier types are also known. In n-channel FETs the dominant carrier type comprises electrons, and in p-channel FETs the dominant carrier type comprises holes. Both n-channel and p-channel FETs can be fabricated as either enhancement mode or depletion mode devices.
Thin film transistor performance depends upon material characteristics as well as the geometry of the transistor. The conductance between the source and the drain of a field effect transistor depends upon the gate voltage (Vg), the drain-source voltage (Vds), and a threshold voltage of the device (VT). VT is positive for enhancement mode FETs, and is negative for depletion mode FETs. For n-type enhancement mode FETs, the conductance increases with increasingly positive gate voltage, and with increasing drain-source voltage. When Vds, for (Vds greater than 0), exceeds the quantity (VGSxe2x88x92VT) in magnitude, the FET is in saturation (i.e., fully into accumulation mode), and the saturated drain current (IDSsat) is given approximately by:                               I          DS          sat                =                              W                          2              ⁢              L                                ⁢                      xe2x80x83                    ⁢                      C            g                    ⁢                                    μ              ⁡                              (                                                      V                    G                                    -                                      V                    T                                                  )                                      2                                              (        1        )            
where VT is the threshold voltage, Cg is the capacitance per area of the gate insulator, xe2x96xa1 is the field effect mobility of the dominant charge carrier, and W and L are the channel width and length, respectively (see FIG. 2). IDS depends upon the conductivity of the semiconductor as well as the dimensions of the FET. For a p-channel enhancement mode FET, the voltage senses are reversed from those in an n-channel enhancement mode FET.
In this disclosure a pixel layout is detailed that includes a novel transistor design that can enable alternative processing schemes for fabricating the backplane as well as enabling the use of active matrix backplanes in certain types of displays where a large amount of current is needed to drive each pixel.
In one aspect, the invention features a transistor for use with an electronic display comprising a plurality of pixels. The transistor comprises a substrate, a gate electrode and a gate dielectric in contact with the gate electrode, a semiconductor layer, and a pixel electrode and a data line electrode in contact with the semiconductor layer. The pixel electrode and the data line electrode define a channel, the channel has a length, defined as the distance between the pixel and data line electrodes, greater than about 10 microns, and preferably about 25 microns.
In one embodiment, the gate electrode is adjacent the substrate, the gate dielectric is adjacent the gate electrode, the semiconductor layer is adjacent the gate dielectric, and the pixel and data line electrodes are adjacent the semiconductor layer. In another embodiment, the gate electrode is adjacent the substrate, the gate dielectric is adjacent the gate electrode, the pixel and data line electrodes are adjacent the gate dielectric, and the semiconductor is adjacent the pixel and data line electrodes. In still another embodiment, the pixel and data line electrodes are adjacent the substrate, the semiconductor layer is adjacent the pixel and data line electrodes, the gate dielectric is adjacent the semiconductor layer, and the gate electrode is adjacent the gate dielectric. In still another embodiment, the semiconductor layer is adjacent the substrate, the pixel and data line electrodes are adjacent the semiconductor layer, the gate dielectric is adjacent the semiconductor layer, and the gate electrode is adjacent the gate dielectric.
In one embodiment, the pixel electrode is a selected one of a source electrode and a drain electrode of the transistor. In one embodiment, the pixel electrode and the data line electrode are interdigitated. In one embodiment the data line electrode comprises a data line of the display.
In another embodiment, the pixel electrode and the data line electrode are constructed so as to define a spiral shape therebetween. In another embodiment, the pixel electrode and the data line electrode define a transistor channel that is a non-rectilinear shape. In one embodiment, the transistor is a field effect transistor.
In one embodiment, the semiconductor layer comprises an organic semiconductor layer. For example, the semiconductor layer can comprise regioregular poly(3-hexyl thiophene), polythiophene, poly(3-alkylthiophene), alkyl-substituted oligothiophene, polythienylenevinylene, poly(para-phenylenevinylene) and doped versions of these polymers, and oligomeric semiconductors such as alpha-hexathienylene.
In one embodiment, the shape of the channel provides a given W/L ratio when the value of the dimension L is defined by a deposition technology chosen from screen printing, stencil printing, ink jet printing, flexo-gravure printing and offset printing. The shape of the channel can provide a W/L ratio that is selected based upon the majority carrier conductivity of a semiconductor. Alternatively, the shape of the channel can provide a W/L ratio that is selected based upon the minority carrier conductivity of a semiconductor.
In another aspect, the invention features an electronic display drive circuit. The electronic display drive circuit comprises a display electrode, an insulator disposed adjacent the display electrode, and a transistor placed adjacent to the insulator substantially underneath the display electrode for addressing the display electrode. The insulator can be at least five microns in thickness. The insulator insulates a pixel electrode and a data line electrode of the transistor from the display electrode except for a region of electrical contact between the pixel electrode of the transistor and the display electrode.
In one embodiment, the transistor comprises a pixel electrode and a data line electrode, a semiconductor layer adjacent the pixel electrode and data line electrode, a gate electrode and a gate dielectric separating the semiconductor from the gate electrode.
In one embodiment, the pixel electrode and the data line electrode are interdigitated. In another example, the electronic display further comprises a plurality of data lines and select lines, wherein extensions of the data lines form a plurality of data line electrodes and extensions of the select lines form a plurality of gate electrodes. In still another example, the gate electrode comprises a bar and fingers extending from the bar.
In another embodiment, the pixel electrode and the data line electrode jointly define a channel having a spiral shape. In still another embodiment, the pixel electrode and the data line electrode define a transistor channel that is a non-rectilinear shape. In one embodiment, the channel between the pixel electrode and the data line electrode has a length greater than about 25 microns.
In one embodiment, the semiconductor layer comprises an organic semiconductor layer. For example, the semiconductor layer can comprises regioregular poly(3-hexyl thiophene).
In one embodiment, the electronic display drive circuit further comprises a storage capacitor comprising a portion of the pixel electrode and a portion of a select line or another conductive element near the pixel electrode. In one example, the storage capacitor further comprises a portion of the insulator disposed between the portion of the pixel electrode and the portion of the select line or another conductive element near the pixel electrode.
In another embodiment, the electronic display further comprises a display media comprising one of electrophoretic particles, rotating balls, suspended needles, and bichromal spheres. Alternatively, the electronic display further comprises a display media comprising liquid crystals or electroluminescent particles. In another embodiment, the electronic display further comprises a light emitting diode.
In one aspect, the invention features a method of fabricating a transistor, comprising the step of printing at least one structural element of a transistor, using a process chosen from screen printing, ink jet printing, printing through a stencil, flexo-gravure printing and offset printing. In one embodiment, the step of printing comprises printing a first electrode and a second electrode, said first electrode and said second electrode defining in a semiconductor a channel having a length L of at least 10 microns. In one embodiment, the channel length L is at least about 25 microns. In another embodiment, the channel is non-rectangular in shape.
The foregoing and other objects, aspects, features, and advantages of the invention will become more apparent from the following description and from the claims.